The future of compute starts with how we design it.
An AI agent for chip physical design, from a single die to a 3D stack.
- SRAM
- Core
- NPU
- PHY
memory
- nothing stored yet
- WNS
- –
- TNS
- –
- DRC
- –
- Congestion
- –
Chips went to 3D,
EDA should too
Logic, memory and I/O now ship as stacked dies. Most tools still treat each die as a flat chip, so the stack is closed by hand.
- Partitioning
- Which blocks go on which die, and what every crossing costs.
- Cross-die timing
- Paths that start on one tier and end on another.
- Heat and power
- A hot logic die under memory changes what will close.
- Bonds and TSVs
- The interface between dies is now part of the floorplan.
We’re building Archgen to work on the whole stack as one design.
Inside a run
One terminal, one block: what the agent reads, changes and keeps.
top_ctrl
rtl
flow
logs
memory
- block_7.fix
- block_9.fix
reports
- timing.rpt
- drc.rpt
@archgen why is block_7 failing timing?
↳ Found it: the SRAM macro sits too far from the arbiter. Moving it and rerunning.
@archgen fix the congestion near the SRAM macros
↳ Patched floorplan.tcl. Rerun queued.
@archgen triage tonight’s DRC report
↳ Triaged. 3 real violations left for review; the rest share one spacing rule.
@archgen what did we learn on the last block?
↳ Wider macro halos cleared the congestion. Applied to block_9.
@archgen summarise the overnight runs for the team
↳ Posted to #pd-signoff.
@archgen can this core close at the target clock?
↳ Not at 72% utilization. At 66% it closes with slack to spare.
Blog
-
Read
How We Ranked First in the HRT (Hudson River Trading) and Partcl Macro Placement Challenge
A technical write-up of the approach behind our verified rank-1 score on the IBM macro-placement benchmarks.
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Read
Why Chip Design Still Takes 18 Months, and What AI Can Actually Fix
The semiconductor industry designs chips the same way it did a decade ago. Placement is only 20% of the problem. Here's what AI needs to fix to actually ship chips faster.
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Read
Cognitive Agents for the Next Era of Silicon
Marrying Reinforcement Learning with Agentic Reasoning to accelerate Physical Design (PD). How PD Code closes timing on real RISC-V processors in weeks rather than months.
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Read
On Disrupting the Semiconductor Industry with AI Agents
Accelerating chip design of CPUs, GPUs and TPUs using an ecosystem of AI agents. How we're building ChipOS to automate the Spec-to-GDSII development flow.
Let’s talk silicon.
Pick a time to meet us.